Design of the hottest zero current zero voltage sw

Research on zero current zero voltage switching interleaved double switch forward converter

1 introduction

double switch forward converter has the advantages of low switching voltage stress, no danger of bridge arm straight through, and high reliability. However, one of its outstanding shortcomings is that its duty cycle is less than 0.5, which leads to large voltage and current fluctuations of the rectifier output, making the filter larger. In order to overcome this shortcoming, the staggered parallel structure can be adopted. For the output end, there are two parallel modes: one is parallel at the output filter capacitor side, and the other is parallel at the freewheeling diode side. The latter is better than the former, because when the output current pulsation is the same, the filter inductance in parallel on the freewheeling diode side is 1/2 of the filter inductance in parallel on the output filter capacitor side. The circuit topology studied in this paper is shown in Figure 1. Using interleaving control can improve the equivalent output duty cycle, increase the equivalent frequency of the converter, reduce the output current ripple, and then reduce the volume of the filter [1]

Figure 1 Schematic diagram of interleaved parallel dual switch forward converter

in order to suppress the voltage spike caused by transformer leakage inductance when the switch is turned off, LCD lossless absorption network is used in the circuit topology in Figure 1 [2]

2 Analysis of working process

after the two secondary sides of the transformer of the two converters are interleaved in parallel, they are connected in series at the output filter capacitor. In order to simplify the analysis, only one secondary side of each transformer is drawn in the switch mode equivalent circuit in Figure 2. Assuming that all switches and diodes are ideal devices, considering the commutation process of the freewheeling diode and rectifier diode at the output of the transformer, the junction capacitance between the drain and source of the MOSFET is CS; C1=C2，L1=L2； Transformer ratio n=n1/n2, and the leakage inductance of both transformers is LK; The filter inductance is large enough so that the filter inductance, filter capacitor and load resistance can be regarded as a constant current source with current io

(a) mode 1

(b) mode 2

(c) mode 3

(d) mode 4

(E) mode 5

(f) mode 6

(g) mode 7

Figure 2 the equivalent circuit of each switch mode

in the first half, there are 7 switch modes in the circuit topology, and the corresponding equivalent circuit is shown in Figure 2. The second half of the switching cycle is similar. See Figure 3 for the main waveform

Figure 3 main waveform diagram

2.1 switching mode 1 [t0 - T1]

before t0 time, the voltage on S1 is uds1, the voltage on S2 is uds2, and uds1 uds2. Its size will be explained later. Transformer T2 is magnetically reset through D3 and D4. At T0, S1 and S2 are opened at the same time. Because the transformer has a certain leakage inductance, the primary side current of transformer T1 gradually increases from zero to 2io/n, and IO is converted from D11 to D9. At this time, the initial voltage on C1 is - UC, and UC UIN, while L1, C1 and D5 resonate through S1. This switching mode ends when the primary side current of transformer T1 reaches 2io/N, and the duration is

t1-t0= (1)

2.2 switching mode 2 [T1-T2]

transformer T2 continues magnetic reset. L1, C1 and D5 continue to resonate through S1 until the voltage on capacitor C1 changes from - UC to + UC, and this switching mode ends

2.3 switch mode 3 [T2 － T3]

s1, S2 continues to open. Transformer T2 continues magnetic reset until ilm2=0, and this switch mode ends

2.4 switch mode 4 [T3 － T4]

s1, S2 continues to open. L2 is small relative to LM2, which can be ignored here. Transformer T2 primary excitation inductance LM2, leakage inductance LK2, junction capacitors CS3, CS4, C2 and D7 of S3 and S4 are resonated by UIN. From the circuit structure, it can be seen that the junction capacitance CS3 of C2 and S3 is equivalent to parallel connection, and C2 is much larger than the junction capacitance CS3, so the voltage drop speed on S3 is much slower than that of S4

2.5 switch mode 5[t4-t5]

t4, S1 and S2 are turned off at zero voltage. When D6 is turned on, the load current 2io/n and excitation current IM1 converted to the primary side charge the junction capacitors CS1 and CS2 of S1 and S2, and C1 is discharged at the same time. Transformer T2 primary excitation inductance LM2, leakage inductance LK2, junction capacitors CS3, CS4, C2 and D7 of S3 and S4 continue to resonate through UIN. This switching mode ends when uc1=0, uds1=uds2=uin/2, and the duration is:

t5-t4= (2)

2.6 switching mode 6[t5-t6]

s1, the junction capacitance CS1 and CS2 of S2 continue to be charged, C1 continues to be discharged, so that the primary side of transformer T1 bears back voltage, D9 is turned off, D11 continues to flow, and there is only excitation current IM1 in the primary side of transformer T1. The excitation inductance LM2 on the primary side of transformer T2, the leakage inductance LK2, the junction capacitors CS3, CS4, C2 and D7 of S3 and S4 continue to resonate through UIN. The voltage at the same end of T2 is positive, and D9 and D11 are opened at the same time. The excitation current ilm2 of T2 flows through D9, clamping the secondary side of transformer T2 at zero, making uds4 uc=uds3 UIN, and remains unchanged until the next opening

2.7 switch mode 7 [T6 － T7]

at time T6, uds1=uds2=uin, uc1=－ UIN, uc2=－ UC, D1 and D2 are opened, and transformer T1 is magnetically reset through D1 and D2 until S3 and S4 are opened at the same time, that is, at the beginning of the second half cycle

3 experimental results

AZ Harding said

3.1 the main parameters of the circuit

uin=270v; Uout=360V； Po=2kW； fs=50kHz； Transformation ratio n=1.08; Llk=5 H； Lm=2.7mH。

3.2 experimental waveform

experimental waveform is shown in Figure 4 and Figure 6. Figure 4 shows the current waveform of the primary side and the voltage waveform on switch S1. When turned on, the current in the switch tube gradually increases from zero. After the switch tube is turned off with ZVS, the primary side charges the drain source junction capacitor of the switch tube with constant current. Figure 5 and Figure 6 show the driving voltage and the voltage waveform on switches S1 and S2 respectively. It can be seen that the voltage on the upper tube S1 decreases little and the voltage on the lower tube S2 decreases a lot in the late stage of switching off of switches S1 and S2

Figure 4 primary side current and switch S1 voltage waveform

Figure 5 drive voltage and switch S1 voltage waveform

Figure 6 drive voltage and switch S2 voltage waveform

3.3 efficiency

the 2KW dc/dc converter developed by us has an efficiency of 92.1% at full load

4 conclusion

1) with the help of the leakage inductance with low thermal conductivity of the transformer, the ZCS is turned on, and the irfp460 is used as the switch tube to realize the ZVS turn off

2) LCD clamping network suppresses the voltage spike on the switch tube caused by transformer leakage inductance during shutdown